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1 www.pericom.com p-0.1 10/12/2011 pi6c20400b block diagram pin confguration description pericom semiconductor's pi6c20400b is a pcie 3.0 compliant high-speed, low-noise diferential clock bufer designed to be companion to pcie 3.0 clock generator. it is backward compat - ible with pcie 1.0 and 2.0 specifcation. te device distributes the diferential src clock from pcie 3.0 clock generator to four diferential pairs of clock outputs either with or without pll. te clock outputs are controlled by input selection of src_stop#, pwrdwn# and smbus, sclk and sda. when input of either src_stop# or pwrdwn# is low, the output clocks are tristated. when pwrdwn# is low, the sda and sclk inputs must be tri-stated. features ? phase jitter flter for pcie 3.0 application ? four pairs of diferential clocks ? low skew < 50ps ? low jitter < 50ps cycle-to-cycle ? < 1 ps additive rms phase jitter ? output enable for all outputs ? outputs tristate control via smbus ? programmable pll bandwidth ? 100 mhz pll mode operation ? 100 - 400 mhz bypass mode operation ? 3.3v operation ? packaging (pb-free and green): -28-pin ssop (h28) -28-pin tssop (l28) 1:4 clock driver for intel pcie? 3.0 chipsets out0 out0# out1 out1# out2 out2# out3 out3# div output control smbus controller pll pll_bw# src src# pll/byp ass# sclk sda oe_inv oe_0 & oe_3 src_st op# pwrdwn# v dd_a v ss_ a i ref oe_inv v dd out3 out3# oe_3 out2 out2# v dd pll_bw # src_stop# pwrdwn# 28 27 26 25 24 23 22 21 20 19 18 17 16 15 1 2 3 4 5 6 7 8 9 10 11 12 13 14 v dd src src# v ss v dd out0 out0# oe_0 out1 out1# v dd pll/bypass# sclk sda 11-0126
2 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets serial data interface (smbus) pi6c20400b is a slave only smbus device that supports indexed block read and indexed block write protocol using a single 7-bit ad - dress and read/write bit as shown below. pinout table pin name type pin no description src & src# input 2, 3 0.7v diferential src input from pi6c410 clock synthesizer oe_0 & oe_3 input 8, 21 3.3v lvttl input for enabling outputs, active high. oe_0 for out0 / out0# oe_3 for out3 / out3# oe_inv input 25 3.3v lvttl input for inverting the oe, src_stop# and pwrdwn# pins. when 0 = same stage when 1 = oe_0, oe_3, src_stop#, pwrdwn# inverted. out[0:3] & out[0:3]# output 6, 7, 9, 10, 19, 20, 22, 23 0.7v diferential outputs pll/bypass# input 12 3.3v lvttl input for selecting fan-out of pll operation. sclk input 13 smbus compatible sclock input sda i/o 14 smbus compatible sdata iref input 26 external resistor connection to set the diferential output current src_stop# input 16 3.3v lvttl input for src stop, active low pll_bw# input 17 3.3v lvttl input for selecting the pll bandwidth pwrdwn# input 15 3.3v lvttl input for power down operation, active low v dd power 1, 5, 11, 18, 24 3.3v power supply for outputs vss ground 4 ground for outputs vss_a ground 27 ground for pll vdd_a power 28 3.3v power supply for pll address assignment a6 a5 a4 a3 a2 a1 a0 r/w 1 1 0 1 1 1 0 0/1 data protocol 1 bit 7 bits 1 1 8 bits 1 8 bits 1 8 bits 1 8 bits 1 1 bit start bit slave addr r/w ack register ofset ack byte count = n ack data byte 0 ack data byte n - 1 ack stop bit notes: 1. register ofset for indicating the starting register for indexed block write and indexed block read. byte count in write mode cannot be 0. 11-0126
3 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets data byte 0: control register bit descriptions type power up condition output(s) afected source pin 0 outputs mode 0 = divide by 2 1 = normal rw 1 = normal out[0:3], out[0:3]# na 1 pll/bypass# 0 = fanout 1 = pll rw 1 = pll out[0:3], out[0:3]# na 2 pll bandwidth 0 = high bandwidth, 1 = low bandwidth rw 1 = low out[0:3], out[0:3]# na 3 reserved na 4 reserved na 5 reserved na 6 src_stop# 0 = driven when stopped 1 = tristate rw 0 = driven when stopped out[0:3], out[0:3]# na 7 pwrdwn# 0 = driven when stopped 1 = tristate rw 0 = driven when stopped out[0:3], out[0:3]# na data byte 1: control register bit descriptions type power up condition output(s) afected source pin 0 reserved na 1 outputs enable 1 = enabled 0 = disabled rw 1 = enabled out0, out0# na 2 rw 1 = enabled out1, out1# na 3 reserved na 4 reserved na 5 outputs enable 1 = enabled 0 = disabled rw 1 = enabled out2, out2# na 6 rw 1 = enabled out3, out3# na 7 reserved na 11-0126
4 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets data byte 2: control register bit descriptions type power up condition output(s) afected source pin 0 reserved na 1 allow control of outputs with assertion of src_stop# 0 = free running 1 = stopped with src_stop# rw 0 = free running out0, out0# na 2 rw 0 = free running out1, out1# na 3 reserved na 4 reserved na 5 allow control of outputs with assertion of src_stop# 0 = free running 1 = stopped with src_stop# rw 0 = free running out2, out2# na 6 rw 0 = free running out3, out3# na 7 reserved na data byte 3: control register bit descriptions type power up condition output(s) afected source pin 0 reserved rw 1 rw 2 rw 3 rw 4 rw 5 rw 6 rw 7 rw data byte 3: control register bit descriptions type power up condition output(s) afected pin 0 pericom id r 0 na na 1 r 0 na na 2 r 0 na na 3 r 0 na na 4 r 0 na na 5 r 1 na na 6 r 0 na na 7 r 0 na na 11-0126
5 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets functionality pwrdwn# out out# src_stop# out out# 1 normal normal 1 normal normal 0 i ref 2 or float low 0 i ref 6 or float low power down (pwrdwn# assertion) power down (pwrdwn# de-assertion) pwrdwn# out# out pwrdwn# out out# tdrive_pwrdwn# <300us, >200mv tstable <1ms figure 1. power down sequence figure 2. power down de-assert sequence 11-0126
6 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets diferential clock output current board target trace/term z reference r, iref = v dd /(3xrr) output current v oh @ z 100f (100f diferential 15% coupling ratio) r ref = 475f 1%, i ref = 2.32ma i oh = 6 x i ref 0.7v @ 50 0v i out 0.85v slope ~ 1/rs r o r os v out = 0.85v max iout v dd (3.3v 5%) current-mode output bufer characteristics of out[0:3], out[0:3]# diferential clock bufer characteristics symbol minimum maximum r o 3000f n/a r os unspecifed unspecifed v out n/a 850mv current accuracy symbol conditions confguration load min. max. i out v dd = 3.30 5% r ref = 475f 1% i ref = 2.32ma nominal test load for given confguration -12% i nominal +12% i nominal note: 1. i nominal refers to the expected current based on the confguration of the device. 11-0126
7 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets absolute maximum ratings (over operating free-air temperature range) symbol parameters min. max. units v dd_a 3.3v core supply voltage -0.5 4.6 v v dd 3.3v i/o supply voltage -0.5 4.6 v ih input high voltage 4.6 v il input low voltage -0.5 ts storage temperature -65 150 c v esd esd protection 2000 v note: 1. stress beyond those listed under absolute maximum ratings may cause permanent damage to the device. dc electrical characteristics (v dd = 3.35%, v dd_a = 3.35%) symbol parameters condition min. max. units v dd_a 3.3v core supply voltage 3.135 3.465 v v dd 3.3v i/o supply voltage 3.135 3.465 v ih 3.3v input high voltage v dd 2.0 v dd + 0.3 v il 3.3v input low voltage v ss C 0.3 0.8 i il input leakage current 0 < v in < v dd -5 +5 a v oh 3.3v output high voltage i oh = -1ma 2.4 v v ol 3.3v output low voltage i ol = 1ma 0.4 i oh output high current i oh = 6 x i ref , i ref = 2.32ma 12.2 ma 15.6 c in input pin capacitance 2 5 pf c out output pin capacitance 6 l pin pin inductance 7 nh i dd(bypass) power supply current (pll bypass) v dd = 3.465v, f cpu = 100mhz 90 ma i dd power supply current v dd = 3.465v bypass mode 100 f cpu = 100mhz pll mode 130 i ss power down current driven outputs 40 i ss power down current tristate outputs 12 t a ambient temperature -40 85 c 11-0126
8 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets ac switching characteristics (v dd = 3.35%, v dd_a = 3.35%) symbol parameters condition min typ. max. units notes f in pll mode 95 105 mhz bypass mode 100 400 mhz t rise / t fall rise and fall time (measured be - tween 0.175v to 0.525v) 175 700 ps 2 dt rise / dt fall rise and fall time variation 125 ps 2 t pd pll mode 250 ps non-pll mode 2.5 6.5 ns t jitter cycle C cycle jitter 50 ps 3, 4 v high voltage high including overshoot 660 1150 mv 2 v low voltage low including undershoot -300 mv 2 v cross absolute crossing point voltages 250 550 mv 2 dv cross total variation of vcross over all edges 140 mv 2 t dc duty cycle 45 55 % 3 t jphpcieg1 phase jitter, pll mode pcie gen1 30 86 ps (p-p) t jphpcieg2 pcie_2_0_8mhz_1_5m_h3_step, low freq. 0.7 3 ps (rms) pcie_2_0_8mhz_1_5m_h3_step, high freq. 2 3.1 t jphpcieg3 pcie_3_0_2mhz_5m_h3_first, low freq. 2 3 pcie_3_0_2mhz_5m_h3_first, high freq. 0.47 1 t jphpcieg1 additive phase jitter, bypass mode pcie gen1 0 0.001 ps (p-p) t jphpcieg2 pcie_2_0_8mhz_1_5m_h3_ first, low freq. 0 0.001 ps (rms) pcie_2_0_8mhz_1_5m_h3_ first, high freq. 0 0.001 t jphpcieg3 pcie_3_0_2mhz_5m_h3_first, low freq. 0 0.001 pcie_3_0_2mhz_5m_h3_first, high freq. 0 0.001 notes: 1. test confguration is r s = 33.2f, rp = 49.9f, and 2pf. 2. measurement taken from single ended waveform. 3. measurement taken from diferential waveform. 4. measurement taken using m1 data capture analysis tool. 5. additive jitter is calculated from input and output rms phase jitter by using pcie 2.0 flter. (t jadd = (output jitter) 2 C (input jitter) 2 11-0126
9 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets confguration test load board termination 475? 1% 49.9? 1% rp 49.9? 1% rp 33? 5% rs 33? 5% rs pi6c20400b tla tlb out out# 2pf 5% 2pf 5% 11-0126
10 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets packaging mechanical: 28-pin ssop (h) 1 : 28-pin, 209-mil wide, ssop n o i t p i r c s e d : e d o c e g a k c a p 1250 - d p : # l o r t n o c t n e m u c o d f : n o i s i v e r 8 0 / 0 1 / 4 0 : e t a d h28 08-0143 11-0126
11 www.pericom.com p-0.1 10/12/2011 pi6c20400b 1:4 clock driver for intel pcie? 3.0 chipsets pericom semiconductor corporation ? 1-800-435-2336 packaging mechanical: 28-pin tssop (l) 1 description: 28-pin, 173-mil wide, tssop package code: l document control no. pd - 1313 revision: d date: 03/09/05 pericom semiconductor corporation 3545 n. 1st street, san jose, ca 95134 1-800-435-2335 ? www.pericom.com .378 .386 .047 1.20 .002 .006 seating plane .0256 bsc .018 .030 .252 bsc 1 28 .169 .177 0.05 0.15 6.4 0.45 0.75 0.09 0.20 4.3 4.5 9.6 9.8 0.65 0.19 0.30 .007 .012 .004 .008 max note: 1. package outline exclusive of mold flash and metal burr 2. controlling dimentions in millimeters 3. ref: jedec mo-153f/ae ordering information (1-3) ordering code package code package description pi6c20400bhe he 28-pin, 209-mil wide, ssop, pb-free and green PI6C20400BLE le 28-pin, 173-mil wide, tssop, pb-free and green notes: 1. 1termal characteristics can be found on the company web site at www.pericom.com/packaging/ 2. e = pb-free and green 3. adding an x sufx = tape/reel 11-0126

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